Phase-locked loop (PLL) circuits are useful in many electronic systems. Example application for PLL circuits include master clock generation for a microprocessor system, clock generation for a sampling clock in an analog-to-digital conversion system, clock generation for data recovery in a low-voltage differential signal (LVDS) driver/receiver system, as well as numerous other applications.
PLL applications typically provide an output clock signal by comparing the output clock signal to a reference clock signal. A phase-frequency detector (PFD) circuit is often employed to provide a raw control signal to a loop filter. The phase-frequency detector circuit provides the raw control signal in response to comparing the phase and frequency of the output clock signal to the reference clock signal. The loop filter often is a low-pass filter (LPF) that is arranged to provide a smoothed or averaged control signal in response to raw control signal. A voltage-controlled oscillator (VCO) is arranged to receive the control signal from the loop filter. The VCO produces the clock signal in response to the control signal such that the frequency of the clock is varied until the phase and frequency of the clock signal are matched to the reference clock signal.
One example PLL circuit includes a PFD circuit that provides UP and DOWN signals in response to the comparison between the output clock signal and the reference clock signal. The UP signal is active when the frequency of the output clock signal is low, while the DOWN signal is active when the frequency of the output clock signal is determined to be high. Similarly, the UP signal is active when the phase of the output clock is lagging behind the phase of the reference clock, and the DOWN signal is active when the phase of the output clock is leading the phase of the reference clock.